• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The operation of the phase-locked loop comprises a starting phase comprising -a supply to a phase comparator (PFD) of the loop, of a reference signal (CKin / 2) having a duty cycle of 50%, - a reinitialization, at each edge of a first type of the reference signal, of a first divider (DV1) of the output signal of the voltage-controlled oscillator of the loop (VCO), - an output by the phase comparator receiving the reference signal (CKin / 2) and a return signal (CKfb / 2) from said first divider, at each edge of a second type of the reference signal, a control pulse (IMP) during which the control voltage (Vcontrol) of the oscillator increases. Figure for the abstract: Fig 1
    公开号:FR3098665A1
    申请号:FR1907661
    申请日:2019-07-09
    公开日:2021-01-15
    发明作者:Bruno Gailhard；Laurent Truphemus；Christophe Eva
    申请人:STMicroelectronics Rousset SAS；
    IPC主号:
    专利说明:

    [0001] Modes of implementation and embodiments of the invention relate to integrated circuits, and in particular phase-locked loops, commonly referred to by those skilled in the art by the Anglo-Saxon term "Phase-locked loop", and more particularly the management of their start-up.
    [0002] Phase-locked loops are generally used in digital systems requiring a high internal working frequency, for example of the order of several hundred megahertz.
    [0003] Phase-locked loops therefore have the particular role of delivering to these digital systems, for example a programmable core or a microprocessor, an internal clock signal having a high working frequency.
    [0004] However, due to the presence of the feedback loop and the capacitive network necessary for the stability of the phase-locked loop, the starting time, i.e. the time after which the loop is stabilized , with the reference signal and the oscillator output signal close to mutual synchronization, can be very long, typically longer than 100 μs.
    [0005] Furthermore, during this start-up phase, there is a frequency peak (“frequency overshoot”) on the output signal of the loop oscillator, compared to its nominal final value. And this frequency peak can reach up to 25% of the nominal final value.
    [0006] Such a frequency peak at startup implies that the digital circuit of the PLL supports such a frequency. The speed of this circuit must therefore be increased, which in particular induces an increase in leakage currents and/or dynamic consumption.
    [0007] There is therefore a need to limit the starting time of a phase-locked loop as well as the amplitude of this frequency peak.
    [0008] According to one aspect, a method for managing the operation of a phase-locked loop is proposed.
    [0009] The operation of the phase-locked loop includes a start-up phase or step comprising:
    [0010] - delivery to a loop phase comparator of a reference signal having a duty cycle of 50%,
    [0011] a reinitialization, at each edge of a first type, for example at each rising edge, of the reference signal, of a first divider of the output signal of the voltage-controlled oscillator of the loop,
    [0012] -a delivery by the phase comparator receiving the reference signal and a return signal from the first divider, at each edge of a second type, for example at each falling edge, of the reference signal, of a control pulse during which the oscillator control voltage increases.
    [0013] The combination of these characteristics, and in particular the supply of a reference signal having a duty cycle of 50%, and a reinitialization of the divider of the loop at each rising edge (for example) of the reference signal allows a significant reduction in the loop start time and frequency overshoot.
    [0014] Thus, as an indication, for a frequency of the reference signal equal to 2, 4, 8 or 16 MHz and a nominal frequency of the output signal of the oscillator equal to 832 MHz, one obtains a starting time of the order from thirty microseconds against a starting time of 70 to more than 100 microseconds for a classic locked loop.
    [0015] Similarly, a frequency peak (frequency overshoot) is obtained on the output signal of the oscillator of the order of a few percent, for example of the order of 2%, against up to 25% for a loop at classic phase lock.
    [0016] In the case where one is in the presence of an initial reference signal not having a duty cycle of 50%, then the delivery of the reference signal advantageously comprises a division by two of this initial reference signal so as to obtain the reference signal having the duty cycle of 50% and, in this case, the return signal is not the output signal coming directly from the first divider of the loop but the output signal from the first divider, divided by two.
    [0017] This allows any initial reference signal to be used, regardless of its duty cycle.
    [0018] While it would be possible for the control pulse delivered by the phase comparator to be used in a charge pump circuit, it is particularly advantageous during the start-up phase, to "short-circuit" this pump circuit charge, to directly apply a precharge current in a resistive capacitive filter connected to the input of the oscillator.
    [0019] In other words, according to such a mode of implementation, during the start-up phase, the increase in the control voltage of the oscillator comprises an application of a precharge current in a resistive capacitive filter connected at the oscillator input.
    [0020] This further contributes to reducing the starting time of the loop and making this starting time less dependent on the current constraints of the charge pump, constraints linked to the stability of the loop.
    [0021] According to one mode of implementation , the resistive-capacitive filter comprises:
    [0022] -a first branch connected between said oscillator input and ground and comprising a resistive network connected in series with a first capacitor having a first capacitive value, said resistive network comprising a first resistor connected between said oscillator input and a intermediate node and having a first resistive value, and a second resistor connected between the intermediate node and the first capacitor and having a second resistive value, and
    [0023] -a second branch connected between said input of the oscillator and ground and comprising a second capacitor having a second capacitive value.
    [0024] The first capacitive value is then advantageously equal to a times the second capacitive value while the first resistive value is equal to a times the second resistive value.
    [0025] The precharge current is then advantageously applied to said intermediate node.
    [0026] A homogeneous increase in the two capacitive voltages at the terminals of the two capacitors is obtained, therefore a stable increase in the capacitive voltage delivered at the input of the oscillator.
    [0027] According to one mode of implementation, the start-up phase ends when the duration of the control pulse is less than a few percent, for example 2%, of the product of the period of the output signal of the oscillator by the ratio division of the first divisor.
    [0028] According to one mode of implementation, when the start-up phase is finished, the output of the phase comparator is connected to a charge pump circuit, the output of which is connected to the input of the voltage-controlled oscillator.
    [0029] In other words, when during the start-up phase, the charge pump circuit has been disconnected and a pre-charge current has been applied to the level of the resistive-capacitive filter, this time it is reconnected at the end of the starting phase, the charge pump circuit to the phase comparator.
    [0030] Of course, if during the start-up phase the charge pump circuit had been left connected to the phase comparator, this connection is not modified at the end of the start-up phase.
    [0031] According to one mode of implementation, when during the start-up phase, the initial reference signal has been divided by two as well as the output signal of the first divider, these divisions by two are no longer carried out when the start-up phase is completed.
    [0032] In other words, when the starting phase is over, the initial reference signal is delivered to the phase comparator while the return signal delivered to the phase comparator is the output signal of the first divider.
    [0033] Furthermore, when the start-up phase is over, it is advantageously possible to carry out a final reset of the first divider on the first edge of a first type, for example the first rising edge, of the reference signal following the end of the start-up phase .
    [0034] This makes it possible to synchronize the reference signal and the return signal coming from the first divider.
    [0035] According to another aspect, an integrated circuit is proposed, comprising a phase-locked loop comprising
    [0036] -a phase comparator, a voltage-controlled oscillator, a first divider connected between the output of the oscillator and a first input of the phase comparator,
    [0037] -delivery means configured to deliver on a second input of the phase comparator, during a start-up phase of the loop, a reference signal having a duty cycle of 50%,
    [0038] -reset means configured to, during said start-up phase, perform on each edge of a first type of the reference signal, a reset of the first divider,
    [0039] the phase comparator being configured to, during said starting phase, deliver, on each edge of a second type of the reference signal, a control pulse, and
    [0040] -control means configured to increase the control voltage of the oscillator during said control pulse.
    [0041] According to one embodiment, the delivery means comprise -an input to receive an initial reference signal, -a divider by two connected to said input, and -an output configured to deliver as a reference signal, the initial reference signal divided by two, and the integrated circuit further comprises another divider by two connected between the output of the first divider and the first input of the phase comparator.
    [0042] According to one embodiment, the control means comprise a current source that can be activated during said pulse and configured to apply, once activated, a precharge current in a resistive-capacitive filter connected to the input of the oscillator.
    [0043] According to one embodiment, the capacitive resistive filter comprises
    [0044] -a first branch connected between said oscillator input and ground and comprising a resistive network connected in series with a first capacitor having a first capacitive value, said resistive network comprising a first resistor connected between said oscillator input and a intermediate node and having a first resistive value and a second resistor connected between the intermediate node and the first capacitor and having a second resistive value, and
    [0045] -a second branch connected between said oscillator input and ground and comprising a second capacitor having a second capacitive value,
    [0046] the first capacitive value being equal to a times the second capacitive value, and the first resistive value is equal to a times the second resistive value, and wherein the current source is connected to said intermediate node.
    [0047] According to one embodiment, the integrated circuit further comprises detection means configured to detect the end of the start-up phase.
    [0048] According to one embodiment, the detection means are configured to detect the duration of the control pulse and/or the nature of the pulse signal delivered by the phase comparator.
    [0049] Thus the detection means can be configured to deliver a signal representative of the end of the start phase when the duration of the control pulse is less than a few percent of the product of the period of the output signal of the oscillator by the ratio of division of the first divisor.
    [0050] As a variant, the detection means can be configured to deliver a signal representative of the end of the start-up phase when the first pulse of the pulse signal delivered by the phase comparator is detected, requesting a reduction in the control voltage of the voltage controlled oscillator.
    [0051] According to one embodiment, the integrated circuit is configured to, when the start-up phase is finished, connect the output of the phase comparator to a charge pump circuit whose output is connected to the input of the oscillator controlled in voltage.
    [0052] According to one embodiment, when the start-up phase is finished, the delivery means are configured to deliver the initial reference signal to the phase comparator, and the integrated circuit comprises control means configured to deactivate said other divider by two, so that the feedback signal delivered to the phase comparator is the output signal of the first divider.
    [0053] According to one embodiment, the reset means are configured to, when the start-up phase is finished, carry out a final reset of the first divider on the first edge of a first type of the reference signal following the end of the start-up phase .
    [0054] Other advantages and characteristics of the invention will appear on examination of the detailed description of the modes of implementation and embodiment of the invention, in no way limiting, and of the appended drawings in which:
    [0055]
    [0056]
    [0057] represent embodiments and embodiments of the invention.
    [0058] In FIG. 1, the reference PLL denotes a phase-locked loop comprising an input BE to receive an initial reference signal CKin and an output terminal BS to deliver the output signal CK VCO delivered by a voltage-controlled oscillator VCO.
    [0059] By way of example, the frequency of the initial reference signal CKin can be equal to 16 MHz while the frequency of the output signal CK VCO can be equal to 832 MHz.
    [0060] Furthermore, the output terminal BS of the phase-locked loop PLL is connected to the input of a first divider DV1, for example a fractional divider, intended to divide by N the signal CK VCO delivered by the local oscillator VCO.
    [0061] The division ratio N is equal to the ratio between the frequency of the signal CK VCO and the frequency of the initial reference signal CKin.
    [0062] By way of example, here, this division ratio is equal to 800/16 or 52. This divider by N is of conventional structure and known per se and is typically formed by a counter resettable by reception on its reset input RST d an IMPRST reset signal or pulse.
    [0063] The output signal of the first divider is referenced CKfb.
    [0064] The phase-locked loop PLL comprises a starting phase or step at the end of which the reference signal delivered at the input of the phase comparator PFD (of conventional and known structure) of the loop and the signal CKfb are almost synchronized. Of course, when the reference signal and the signal CKfb are almost synchronized, the reference signal and the output signal CK VCO are also almost synchronized.
    [0065] The end of this start-up phase occurs here in this example, when a logic signal ENST has for example the logic value "1".
    [0066] It is now assumed in this example that the initial reference signal CKin has any duty cycle, in particular different from 50%.
    [0067] The PLL loop comprises in this respect delivery means MDV configured to deliver on the second input E2 of the phase comparator PFD, the reference signal CKin/2 which is a division by two of the initial reference signal CKin.
    [0068] In this respect, the delivery means here comprise for example a divider by two, DV2A, which is in fact a counter, connected to the input terminal BE and delivering the reference signal CKin/2.
    [0069] The delivery means MDV also comprise a first multiplexer Mux1, controlled by the signal ENST, receiving on the one hand the reference signal CKin/2 and the initial reference signal CKin.
    [0070] During the start-up phase, that is to say when the logic signal ENST has the logic value "0", the multiplexer Mux1 delivers on the input E2 the initial reference signal divided by two which thereby forms the signal reference received on the second input E2 of the phase comparator PFD.
    [0071] The return signal delivered to the first input E1 of the phase comparator PFD comes from a second multiplexer Mux2 also controlled by the signal ENST.
    [0072] The output signal of the first divider CKfb is delivered to a first input of the second multiplexer Mux2.
    [0073] The second input of the second Mux2 receives the signal CKfb/2 delivered by another divider by two DV2B and which consequently results from the division by two of the signal CKfb.
    [0074] Thus, in this example, during the start-up phase of the PLL loop, since the phase comparator input E2 receives the reference signal CKin/2, the return signal delivered to the first input E1 of the phase comparator is the CKfb/2 signal.
    [0075] The phase comparator PFD conventionally delivers, depending on the signals present at its two inputs, either a command pulse UP intended to increase the control or command voltage at the input of the oscillator VCO or a command pulse DOWN intended to reduce this control voltage.
    [0076] The PLL loop also comprises a resistive-capacitive filter FLT having a node ND1 connected to the command or control input of the voltage-controlled oscillator VCO.
    [0077] The phase-locked loop PLL also comprises a charge pump circuit CHP, of conventional structure and known per se, intended to receive the two control pulses UP and DOWN, and delivering a current to the resistive capacitive filter which produces the control voltage Vcontrol applicable to the oscillator input.
    [0078] However, in this embodiment, the phase comparator PFD is connected to the input of the charge pump circuit CHP by a set of first switches SW1 controllable by the logic signal ENST.
    [0079] In another embodiment, the set of first switches SW1 can be replaced by logic gates, one input of which is connected to the logic signal ENST which makes it possible to open the switches internal to the charge pump circuit CHP.
    [0080] Thus, in this embodiment, when the phase-locked loop is in its start-up phase (ENST=0, for example), the switches SW1 are open, disconnecting the charge pump circuit CHP from the outputs of the phase comparator PFD.
    [0081] As illustrated in FIG. 2, the filter FLT here comprises a first branch BR1 connected between the node ND1 and the ground GND and a second branch BR2 also connected between the node ND1 and the ground GND.
    [0082] The first branch comprises a resistive network R connected in series with a first capacitor C1.
    [0083] The resistive network R comprises a first resistor R1 connected between the node ND1 and an intermediate node ND2 and a second resistor R2 connected between the intermediate node ND2 and the first capacitor C1.
    [0084] For the purposes of simplification, C1, C2, R1 and R2 will also designate respectively the capacitive value of the first capacitor C1, the capacitive value of the second capacitor C2, the resistive value of the first resistor R1 and the resistive value of the second resistor R2.
    [0085] In this example, the capacitive value C1 of the first capacitor C1 is equal to a times the capacitive value C2 of the second capacitor C2. As an indication, a is of the order of 10.
    [0086] The resistive value R1 of the first resistor R1 is itself equal to a times the resistive value R2 of the second resistor R2.
    [0087] As a result, the product R2C1 is equal to the product R1C2, i.e. a times the product R2C2.
    [0088] And, during the start-up phase, a precharge current Ip will be applied to the intermediate node ND2.
    [0089] And, since C1 is equal to aC2, it will take the same time to precharge C1 and C2, this time being equal to the filter constant divided by a.
    [0090] As illustrated in Figure 1, this precharge current Ip comes from a current source SC that can be activated via a second switch SW2 controlled by the output of an AND logic gate, referenced PL.
    [0091] This gate PL receives on a first input, the control pulse IMP of the signal UP, and on a second input, the signal ENST inverted by an inverter INV.
    [0092] During the start-up phase, the ENST signal is at “0” and it is at “1” after the start-up phase.
    [0093] Therefore, during the start-up phase, the second switch SW2 is controlled by the pulses of the UP signal, while after the start-up phase, the second switch SW2 is always open.
    [0094] More precisely, during the start-up phase, if the signal UP is at the high level (representative of an IMP pulse), the switch SW2 is closed and the current source delivers the precharge current Ip to the intermediate node ND2.
    [0095] And this lasts as long as the signal UP is at 1, that is to say as long as the control pulse IMP is present.
    [0096] On the other hand, as soon as the pulse IMP disappears (signal UP at zero) the switch SW2 is open and no precharge current is delivered to the node ND2.
    [0097] The capacitive filter FLT is therefore charged during the IMP pulses and these charges make it possible to raise the control voltage at the input of the oscillator VCO, which consequently makes it possible to increase the frequency of the output signal of this oscillator.
    [0098] The current source SC and the filter FLT therefore form part of control means configured to increase the control voltage of the oscillator during said control pulse IMP.
    [0099] The reset of the first divider DV1 is as indicated above obtained by the application of a reset pulse IMPRST on the reset input RST of the divider.
    [0100] This reset pulse IMPRST is obtained, during the start-up phase, by reset means MRST in response to each rising edge FM of the reference signal which here is the signal CKin/2.
    [0101] Of course, it would have been possible to do this reset on each falling edge of the signal CKin/2.
    [0102] Furthermore, as will be seen in more detail below, once the start-up phase is complete, the MRST means will deliver a final reset pulse on the first rising edge of the reference signal, which this time will be the signal CKin, which follows the end of the start-up phase.
    [0103] The MRST reset means can easily be implemented by means of logic circuits.
    [0104] Furthermore, the integrated circuit IC incorporating the phase-locked loop PLL also comprises detection means MDT configured to detect the end of the start-up phase and consequently deliver the logic value 1 to the signal ENST.
    [0105] The end of the starting phase is considered to have been reached when the duration T of the control pulse IMP corresponding to the high state of the "up" signal is less than a few percent of the product of the nominal period T CKVCO of the output signal of the VCO oscillator by the division ratio N.
    [0106] By way of example, this threshold can be taken as equal to 2%.
    [0107] Also, according to a first possibility, to detect this end of start-up phase condition, the detection means MDT can be configured to count the number of edges of the signal CK VCO during the duration of the pulse IMP.
    [0108] According to another possible embodiment, the means MDT may comprise a low-pass filter receiving the signal UP and whose time constant is linked to said threshold by a few percent.
    [0109] Depending on whether or not the output of this filter delivers a high signal, the means MDT will deliver either the logic value “0” or the logic value “1” of the signal ENST.
    [0110] As a variant, the end of the start-up phase can also be considered to have been reached when the first control pulse corresponding to the high state of the “DOWN” signal is detected. Reference is now made more particularly to FIG. 3 to illustrate an embodiment of the method for managing the operation of the PLL loop illustrated in the preceding figures.
    [0111] This figure 3 has the form of a temporal chronogram.
    [0112] On the first line of this figure is represented the initial reference signal CKin which, as can be seen, has a duty cycle different from 50%.
    [0113] On the second line is represented the reference signal CKin/2, resulting from the division by two of the initial reference signal, and which this time has a duty cycle of 50%.
    [0114] This signal CKin/2 is, as explained above, the reference signal delivered to the second input E2 of the phase comparator PFD.
    [0115] Furthermore, it can be seen that at each rising edge of the reference signal CKin/2, is emitted by the means of realization MRST, a realization pulse IMPRST which resets the first divider DV1, that is to say which resets to 0 the counter forming this first divider.
    [0116] Furthermore, on each falling edge of the reference signal CKin/2, the phase comparator PFD compares the phase of the reference signal CKin/2 with the phase of the return signal CKFB/2 and consequently delivers the control pulse IMP of the UP signal.
    [0117] This pulse IMP makes it possible, when it is present, to apply the precharge current Ip to the intermediate node ND2 of the filter FLT.
    [0118] Note that as this start-up phase progresses, the duration of the pulse IMP of the signal UP decreases since the output frequency of the signal CK VCO increases.
    [0119] And, as indicated above, when the duration T of the pulse IMP is less than or equal to 2% of the product of the division ratio N by the period TCK VCO of the oscillator signal, the control signal ENST goes to 1 , marking the end of the start-up phase.
    [0120] At this instant, the first multiplexer Mux1 delivers, on the second input E2 of the phase comparator, the initial reference signal CKin which becomes the reference signal.
    [0121] Furthermore, the return signal delivered to the first input E1 of the phase comparator PFD becomes the signal CKfb coming directly from the divider (i.e. without having been divided by two beforehand).
    [0122] At the same time, the switches SW1 are closed, connecting the two outputs (delivering the two signals UP and DOWN respectively) of the phase comparator PFD to the inputs of the charge pump circuit so as to find the classic operation of a loop at phase lock.
    [0123] Switch SW2 is open, interrupting the application of the precharge current Ip.
    [0124] The current which makes it possible to regulate the control voltage Vcontrol of the local oscillator VCO is this time the current Icp delivered by the charge pump circuit.
    [0125] This being the case, in order to accelerate the synchronization of the signal CK VCO and of the reference signal CKin, the means MRST proceed as indicated above to a final reset of the first divider DV1 during the first rising edge of the reference signal CKin which follows the end of the start-up phase.
    [0126] The phase locked loop will then be ready to deliver its output signal after a few cycles.
    [0127] This output signal could for example be used as a clock signal for a microprocessor.
    权利要求:
    Claims (18)
    [0001]
    Method for managing the operation of a phase locked loop (PLL), the operation of the phase locked loop comprising a starting phase comprising a delivery to a phase comparator (PFD) of the loop, of a reference signal (CKin / 2) having a duty cycle of 50%, a reinitialization, at each edge of a first type of the reference signal, of a first divider (DV1) of the output signal of the voltage-controlled oscillator of the loop (VCO), an output by the phase comparator receiving the reference signal (CKin / 2) and a return signal (CKfb / 2) from said first divider, at each edge of a second type of the reference signal, of a pulse control (IMP) during which the control voltage (Vcontrol) of the oscillator increases.
    [0002]
    A method according to claim 1, wherein outputting said reference signal (CKin / 2) comprises dividing an initial reference signal (CKin) by two and said return signal (CKfb / 2) is the output signal ( CKfb) of the first divider (DV1) divided by two.
    [0003]
    Method according to one of the preceding claims, in which during the starting phase, the increase in the control voltage of the oscillator comprises an application of a precharge current (Ip) in a resistive capacitive filter (FLT ) connected to the oscillator input.
    [0004]
    A method according to claim 3, wherein the resistive capacitive filter (FLT) comprises a first branch (BR1) connected between said input of the oscillator and ground and comprising a resistive network connected in series with a first capacitor having a first capacitive value, said resistive network comprising a first resistor connected between said input of the oscillator and an intermediate node and having a first resistive value and a second resistor connected between the intermediate node and the first capacitor and having a second resistive value, and a second branch (BR2) connected between said input of the oscillator and ground and comprising a second capacitor having a second capacitive value, -the first capacitive value being equal to a times the second capacitive value, and the first resistive value is equal to a times the second resistive value, and wherein said precharge current is applied to said intermediate node.
    [0005]
    Method according to one of the preceding claims, wherein said starting phase ends when the duration (T) of the control pulse (IMP) is less than a few percent of the product of the period of the output signal of the oscillator by the division ratio of the first divisor.
    [0006]
    Method according to one of the preceding claims, in which when the start-up phase is completed, the output of the phase comparator (PFD) is connected to a charge pump circuit (CHP), the output of which is connected to the input of the voltage-controlled oscillator.
    [0007]
    Method according to Claims 2 and 6, in which when the start-up phase is completed, the initial reference signal (CKin) is supplied to the phase comparator (PFD), and the return signal supplied to the phase comparator is the signal of output (CKfb) of the first divider.
    [0008]
    Method according to claim 6 or 7, comprising when the start-up phase is completed, a final reset of the first divider (DV1) on the first edge of a first type of the reference signal following the end of the start-up phase.
    [0009]
    Integrated circuit, comprising a phase locked loop (PLL) comprising -a phase comparator (PFD), a voltage controlled oscillator (VCO), a first divider (DV1) connected between the output of the oscillator and a first input of the phase comparator, delivery means (MDV) configured to deliver to a second input of the phase comparator, during a starting phase of the loop, a reference signal having a duty cycle of 50%, -resetting means (MRST) configured for, during said starting phase, performing at each edge of a first type of the reference signal, a reinitialization of the first divider, the phase comparator being configured for, during said starting phase, delivering, at each edge of a second type of the reference signal, a control pulse, and control means (SC, FLT) configured to increase the control voltage of the oscillator during said pulse.
    [0010]
    An integrated circuit according to claim 9, wherein the means for delivering (MDV) comprises an input for receiving an initial reference signal, a divider-by-two connected to said input, and an output configured to deliver as a reference signal, the initial reference signal divided by two and the integrated circuit further comprises another divider by two connected between the output of the first divider and the first input of the phase comparator.
    [0011]
    Integrated circuit according to one of Claims 9 or 10, in which the control means comprise a current source (SC) which can be activated during said pulse and configured to apply, once activated, a precharge current in a resistive capacitive filter ( FLT) connected to the oscillator input.
    [0012]
    An integrated circuit according to claim 11, wherein the resistive capacitive filter (FLT) comprises a first branch (BR1) connected between said input of the oscillator and ground and comprising a resistive network connected in series with a first capacitor having a first capacitive value, said resistive network comprising a first resistor connected between said input of the oscillator and an intermediate node and having a first resistive value and a second resistor connected between the intermediate node and the first capacitor and having a second resistive value, and a second branch (BR2) connected between said input of the oscillator and ground and comprising a second capacitor having a second capacitive value, -the first capacitive value being equal to a times the second capacitive value, and the first resistive value is equal to a times the second resistive value, and wherein the current source is connected to said intermediate node.
    [0013]
    Integrated circuit according to one of claims 9 to 12, further comprising detection means (MDT) configured to detect the end of the start-up phase.
    [0014]
    Integrated circuit according to claim 13, wherein the detection means (MDT) are configured to detect the duration (T) of the control pulse (IMP) and / or the nature of the pulse signal delivered by the phase comparator.
    [0015]
    An integrated circuit according to claim 14, wherein the detection means are configured to deliver a signal representative of the end of the start-up phase when the duration of the control pulse is less than a few percent of the product of the period of the start-up signal. output of the oscillator by the division ratio of the first divider.
    [0016]
    Integrated circuit according to one of claims 9 to 15, configured for, when the starting phase is finished, connecting the output of the phase comparator (PFD) to a charge pump circuit (CHP) whose output is connected to the voltage controlled oscillator input.
    [0017]
    Integrated circuit according to claims 10 and 16, wherein, when the start-up phase is completed, the delivery means (MDV) are configured to deliver the initial reference signal to the phase comparator, and the integrated circuit comprises control means configured to deactivate said other divider by two, so that the return signal supplied to the phase comparator is the output signal of the first divider.
    [0018]
    Integrated circuit according to claim 16 or 17, wherein the reset means (MRST) are configured to, when the starting phase is completed, perform a final reset of the first divider on the first edge of a first type of the reference signal following the end of the start-up phase.
    类似技术:
    公开号 | 公开日 | 专利标题
    EP3764547A1|2021-01-13|Method for managing the starting of a phase locking loop, and corresponding integrated circuit
    EP0441684B1|1994-12-28|Phase lock circuit and resulting frequency multiplier
    EP1424774B1|2011-08-31|Random number generator
    EP0702862B1|1997-10-08|Process for enhancing the noise immunity of a phase-locked loop and device for applying same.
    FR2811165A1|2002-01-04|TIMING METHOD AND TIMING CIRCUIT WITH DOUBLE PHASE LOCKED LOOPS
    EP0564377B1|1995-07-26|Frequency locked loop
    JP5815999B2|2015-11-17|Phase locked loop
    FR2472308A1|1981-06-26|PULSE GENERATOR FOR HORIZONTAL DEVIATION SYSTEM
    EP0329576B1|1993-04-21|Line synchronisation recognition circuit
    FR2840469A1|2003-12-05|PHASE LOCK LOOP
    FR2959367A1|2011-10-28|BUFFER CIRCUIT FOR HIGH VALUE CAPACITIVE LOAD
    FR2773925A1|1999-07-23|Phase lock loop locking condition detection
    FR3112044A1|2021-12-31|Method for managing the start of a phase-locked loop, and corresponding integrated circuit
    EP0526359B1|1996-09-25|Process and circuit arrangement for synchronising a signal
    FR3050308A1|2017-10-20|METHOD AND DEVICE FOR CONTROLLING AT LEAST ONE CHARGE PUMP CIRCUIT
    FR2879858A1|2006-06-23|METHOD FOR CORRECTING THE PHASE TO BETWEEN TWO ENTRY SIGNALS OF A PHASE LOCKED LOOP AND ASSOCIATED DEVICE
    FR2896641A1|2007-07-27|Voltage controller oscillator calibrating method for frequency synthesizer, involves determining impedance value for modifying output frequency of oscillator so as to correspond to reference frequency, and connecting impedance to oscillator
    EP2057533A1|2009-05-13|Pseudoperiodic logic signal generator
    EP0991194B1|2003-12-03|Process and circuit arrangement for generating a clock signal
    EP1746729A1|2007-01-24|Reference frequency generation device and corresponding electronic circuit
    EP1411638A1|2004-04-21|Method and apparatus for generating a signal having a frequency equal to the product of a reference frequency by a real number
    EP3667922B1|2021-06-23|Oscillator locked by injection with variable load impedance
    FR2587498A1|1987-03-20|Detector of digital phase and/or frequency over a wide range
    FR2879859A1|2006-06-23|Frequency synthesis signal generating method for e.g. cellular mobile telephone, involves successively performing measurement phase and correction phase having oscillator control correction from error signal obtained in measurement phase
    FR2766305A1|1999-01-22|METHOD FOR MULTIPLYING THE FREQUENCY OF A CLOCK SIGNAL WITH CYCLIC CHECK, AND CORRESPONDING DEVICE
    同族专利:
    公开号 | 公开日
    US11115038B2|2021-09-07|
    EP3764547A1|2021-01-13|
    CN112217508A|2021-01-12|
    CN212875774U|2021-04-02|
    FR3098665B1|2021-07-30|
    US20210013893A1|2021-01-14|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5898328A|1996-04-19|1999-04-27|Sony Corporation|PLL circuit having a switched charge pump for charging a loop filter up or down and signal processing apparatus using the same|
    US20020153959A1|1999-09-27|2002-10-24|Edmund Gotz|Phase-locked loop|
    EP1170869A2|2000-06-30|2002-01-09|Nokia Mobile Phones Ltd.|Method and arrangement for setting a frequency|
    US20080036513A1|2006-08-10|2008-02-14|Fujitsu Limited|PLL circuit|
    US5963068A|1997-07-28|1999-10-05|Motorola Inc.|Fast start-up processor clock generation method and system|
    AT460774T|2003-04-02|2010-03-15|Christopher Julian Travis|NUMERICALLY CONTROLLED OSCILLATOR AND METHOD FOR PRODUCING AN EVENT TACT|
    US8378724B2|2010-12-22|2013-02-19|Silicon Laboratories Inc.|Controlling a frequency locked loop|
    WO2012165260A1|2011-05-27|2012-12-06|国立大学法人東京大学|Signal conversion circuit, pll circuit, delay adjustment circuit, and phase control circuit|
    US8723567B1|2011-11-01|2014-05-13|Yen Dang|Adjustable pole and zero location for a second order low pass filter used in a phase lock loop circuit|
    EP3070827A1|2015-03-16|2016-09-21|Alstom Technology Ltd|Start-up of HVDC networks|
    EP3070799B1|2015-03-16|2018-11-21|General Electric Technology GmbH|Start-up of hvdc networks|
    JP2017118371A|2015-12-25|2017-06-29|セイコーエプソン株式会社|Timing signal generation device, electronic apparatus and mobile|
    US10365104B2|2016-05-11|2019-07-30|Murata Manufacturing Co., Ltd.|Digital controller for a MEMS gyroscope|
    US10075173B2|2016-11-22|2018-09-11|Silicon Laboratories Inc.|Digital fast lock for phase-locked loops|
    CN108736894B|2017-04-18|2021-08-06|博通集成电路（上海）股份有限公司|fractional-N frequency synthesizer and method therefor|
    EP3425803B1|2017-07-07|2020-01-01|Nxp B.V.|Chirp generating phase-locked loop|
    US10594262B2|2017-07-16|2020-03-17|Short Circuit Technologies Llc|Apparatus and method of reducing power consumption in a low intermediate frequency radio receiver|
    WO2019147740A1|2018-01-23|2019-08-01|DMF, Inc.|Methods and apparatus for triac-based dimming of leds|
    US10873335B2|2019-05-02|2020-12-22|Apple Inc.|Divider control and reset for phase-locked loops|
    US10763871B1|2019-07-03|2020-09-01|Nxp B.V.|Apparatuses and methods involving phase-error tracking circuits|
    FR3098665B1|2019-07-09|2021-07-30|St Microelectronics Rousset|Method for managing the start of a phase-locked loop, and corresponding integrated circuit|
    EP3787187A1|2019-09-02|2021-03-03|NXP USA, Inc.|Locking technique for phase-locked loop|
    US10833684B1|2020-01-15|2020-11-10|Analog Bits Inc.|Method and circuits for reducing noise in phase-locked loops|FR3098665B1|2019-07-09|2021-07-30|St Microelectronics Rousset|Method for managing the start of a phase-locked loop, and corresponding integrated circuit|
    FR3112044A1|2020-06-24|2021-12-31|StmicroelectronicsSas|Method for managing the start of a phase-locked loop, and corresponding integrated circuit|
    法律状态:
    2020-06-23| PLFP| Fee payment|Year of fee payment: 2 |
    2021-01-15| PLSC| Publication of the preliminary search report|Effective date: 20210115 |
    2021-06-23| PLFP| Fee payment|Year of fee payment: 3 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1907661A|FR3098665B1|2019-07-09|2019-07-09|Method for managing the start of a phase-locked loop, and corresponding integrated circuit|
    FR1907661|2019-07-09|FR1907661A| FR3098665B1|2019-07-09|2019-07-09|Method for managing the start of a phase-locked loop, and corresponding integrated circuit|
    EP20182883.7A| EP3764547A1|2019-07-09|2020-06-29|Method for managing the starting of a phase locking loop, and corresponding integrated circuit|
    US16/923,335| US11115038B2|2019-07-09|2020-07-08|Method for managing the startup of a phase-locked loop and corresponding integrated circuit|
    CN202010657681.4A| CN112217508A|2019-07-09|2020-07-09|Method for managing the start-up of a phase-locked loop and corresponding integrated circuit|
    CN202021337773.6U| CN212875774U|2019-07-09|2020-07-09|Phase-locked loop circuit|
    [返回顶部]